Yes, it is a problem in your SDC. As you can see, the endpoint of your path is output port (not a flip-flop). So, when you type command set_propogated_clock, the tool see the real path (and calculate latency) from input clock port to each flip-flop in your design. But, it does not see the path from input clock port to the output port. Such path does not exist in the block netlist. It only be observable on top level of hierarchy.
So, usually in such case (when you load in the tool only one block of hierarchical design), you may set by command set_clock_latency the clock latency for all output/input ports, the value for this latency you may calculate as average of clock latencies for each flip-flop in your block.
Try to uncomment the commented lines in your SDC code (set_clock_latency and set_clock_transition).