Recently I am doing the post_layout simulation. The av_extracted file generated by AssuraQRC is attached to the pre_layout schematic.
However, the simulation reported the following error (virtuoso ADE explorer):
Errors were discovered by the ghost during the flattening of the hierarchy.
Error (SFE-46): "input.scs" 3745324: The instance of `I4': `xxx' can have up to 6 terminals (but there are 78).
You have 78 terminals but only 6 defined in the subcircuit. I don't have enough knowledge about verilog/vhdl, however define buses width explicite in the module definition.