can anyone tell me how to get the post layout delay of a combinational circuit like adder in cadence?
report_timing is not working and "NO contraints file found" is the message shown
report_timing is the right command, works in cadence innovus and cadence genus. your setup is wrong as you haven't provided an SDC file. that is what the tool is telling you.
report_timing is the right command, works in cadence innovus and cadence genus. your setup is wrong as you haven't provided an SDC file. that is what the tool is telling you.
sir, i am using cadence encounter.
first i dealt with counter design. In that design,i used timing_report command and it worked. i had a constraints file too..
Now i deal with adder circuits,which are purely combinational...what should be the contents of the constraints file,since i donot have a clk signal as input to my system.
Thanks in advance
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also the message shown when using report_timing is "No constrained timing paths. Design may not be constrained or library is miising timing information"
In Synopsys SDC there are commands set_max_delay/set_min_delay - they are for non-sync paths. Try them (or Innovus analogs) for constraining your combinational circuit.