nanisan
Newbie level 3
I have designed a simple state machine in VHDL but when doing the post fit HDL Simulation in ModelSim I am not able to track them in the waveform viewer (I am only able to see the signals/states in the behavioural simulation).
Is there an attribute that I can use so that these signals are also synthesized?
type STATE_TYPE is (IDLE, TEST,ADDR_DECODE, DATA_TRS);
signal prs_state, next_state : STATE_TYPE;
Is there an attribute that I can use so that these signals are also synthesized?
type STATE_TYPE is (IDLE, TEST,ADDR_DECODE, DATA_TRS);
signal prs_state, next_state : STATE_TYPE;