Positive Gate Voltage to N-JFET

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Shashiketan

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What happens when positive gate voltage is applied to N-JFET?.. while applying a -gate voltage it reduces the pinch of voltage as it helps in increasing the depletion region?.. but what about gate voltage being positive? will it not suppress the depletion and increase the pinch off?
 

The input gate of a JFET looks like a diode. When the forward bias increases above about 0.6V the gate will start to conduct current.

Reverse bias on a JFET reduces the drain current. Any forward bias above 0V may increase the drain current slightly above its zero bias current. If you increase the forward voltage to the point that gate current starts to flow, you can damage the transistor.
 

I've seen applications where people deliberately soft-forward-bias
FET (or HEMT) transistors to squeeze a little more channel
conductance out of them. There will be a max gate current
spec that you have to respect. If you can't find a rating then
it would be safest to assume zero, but in practicallity a couple
of hundred mV, couple microamps DC isn't going to break
anything. But beware the crest voltage.
 

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