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pos edge to neg edge is as simple as taking away or adding an inverter. active low reset vs active reset is also as simple as an inverter.
the reset or in your case set is a bit little bit more circuitry, async means its signal isnt clocked in, and so you would run it directly into the latches with the latches having a set bit (can be found in most digital books).
This is pos edge DFF , based on this i attached the asyn active low set, to the top most nand gate i.e. which r vertically placed and to nand gate with Q as output.
Hope you can understand my description. Thanks in advance
Yes, I am designing the standard cell , so to characterize its is more simple and delays will be less in nand compare to transmission gates.
I am giving set input to 2 nand gates,
one NAND which has Q as output
other one is First nand gate in top most latch .