Elephantus
Junior Member level 3
I am interconnecting two FPGA's over LVDS where SERDES modules are used on both ends.
The 7:1 SERDES modules are provided by Xilinx, described in the Xilinx application note xapp485. The clock is not embedded in the data but is transmitted separately with a reduced rate and reconstructed on the receiving end.
I would need to implement these SERDES modules on Lattice XP10 FPGAs. Has anyone tried implementing a 7:1 SERDES on a Lattice XP, or tried to port the Xilinx solution before?
I would appreciate any advice or help.
The 7:1 SERDES modules are provided by Xilinx, described in the Xilinx application note xapp485. The clock is not embedded in the data but is transmitted separately with a reduced rate and reconstructed on the receiving end.
I would need to implement these SERDES modules on Lattice XP10 FPGAs. Has anyone tried implementing a 7:1 SERDES on a Lattice XP, or tried to port the Xilinx solution before?
I would appreciate any advice or help.