the hole code is working well i stored my data in rom but i the Port map is not working that is the result is zero ....
process
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: std_logic_vector(31 downto 0 ) ;
begin
for i in 0 to 9 loop
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
write(out_line,int);
writeline(outfile,out_line );
end loop ;
wait; -- Waits forever
end process;
I haven't declare entity for adder because i'm using Xilinxs Ip core Generator , and thanks my problems got fixed that i changed your code instead of mine , i did not clock problem i think it was because of my process architecture .
By the way any idea why i cant use port map in loop to add 10 rows of may data ?
Thanks .
for i in 0 to 8 loop
g1:adder port map (a => ram(i),b=>t,clk => clk,result =>t);
end loop ;
when i use for loop i get
Syntax error near "loop".
Syntax error near "for ".
GEN_ADDERS : for i in 0 to 8 generate
g1:adder port map (a => ram(i),b=>t,clk => clk,result =>t(i));
end generate;
process(t)
variable Sum: unsigned(31 downto 0);
begin
for i in 0 to 8 loop
Sum := Sum + unsigned(t(i));
end loop;
xout <= std_logic_vector(Sum);
end process;
Thanks for your help kevin ,but my data is floating point and the adder is a pre defined floating point adder , I have the same problem for adding t(i) i should use the adder component by port map .
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then -- Something that resets the accumulated sum to 0
Prev_Sum <= (others => '0'); -- The accumulated sum
i <= 0;
elsif (i <= 8) then
Prev_Sum <= t; -- Save the updated sum
i <= i + 1;
end if;
end if;
end process;
g1 : adder port map (a => ram(i),b=>Prev_Sum,clk => clk,result =>t);
The port map is out of process ?
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