Por circuit

[Myself1247]

Hello everyone, I am trying to design a por with supply voltage- 1.08V to 3.6V, supply current- 1u to 2u and trigger voltage- 0.6V to 0.9V. I am using LBC9 in cadence. I have tried many architectures and currently i have designed a por with NAT mos as current reference. I have done the simulation for strong 125°C and weak -40°C. for strong the trigger is at 480mV and for weak at 888mV. please suggest me how to shift the trigger voltage to atleast 600mV.
circuit description:
initially the NAT current is more than the current due to MN4 hence the net1 is pulled up and output is 0V, since the supply voltage is ramping the current through NM4 will increase and at some point would overpower the NAT current and thats how we get a trigger voltage. The PMOS MP0 is used to add hyteresis to the circuit.
Any suggestion is welcomed.

thanks

 

[dick_freebird]

You do not care about specific Vdd "trigger levels". You care about
whether the reset is getting done. The "load" tends to track the POR
threshold and timing is a don't-care as supply ramp rates are
leisurely by comparison.

Find a way to demonstrate "reset integrity" and -then- set rail level
limits, not the other way around.

"Happiness consists of wanting the right things"

 

[Myself1247]

could you please explain what do you exactly mean by reset integrity and also rail level limits? I am new in this domain and i am not able to comprehend what you meant. I tried to compare the currents at the branch and decide the trigger voltage, but due to the variation of NAT current across process and temperature, I am getting huge range of trigger voltage.

correct me if i am wrong.
thanks