Hi Alex.
That is a good point. Here is a snapshot of the schematic that works. This circuit is an isolated version of a soft-power switch that utilizes a PMOS.
Note again that the Q2 schematic is correct with respect to source and drain...the S, D on the little physical representation is wrong.
An explanation:
At Reset, the PMOS Q2 is off. When PWR_SW and PWR_SW_2 are connected together (maybe through a button), the gate of the pmos is pulled momentarily lower than the threshold of the PMOS Q2 and turns it on, which supplies power to the rest of the circuit. A Micro-controller can then set PWR_SW_uC high to hold the PMOS Q2 on for when the button is released.
When the button is pressed to short PWR_SW, PWR_SW_2 again, current flows (just as it did on reset) to set EINT0 Low through the optoisolator, which is connected to the processor's External Interrupt pin. This initiates the power-down cycle, which also sets PWR_SW_uC low along with other house-keeping tasks.
D1 is necessary to allow the common-cathode node to the optoisolator to be high regardless of the state of the anodes...especially when the left-diode anode is low due to PWR_SW_uC.
Header2 allows for overriding the power to the circuit and maintaining power to the whole circuit: this can be utilized, for example, when the micro-controller is being flashed with new firmware.
I also discovered that R48 needs to be a lower value around 5.1K; 100K is too weak of a pull-down.
Hope this helps someone who is looking to incorporate an isolated 'soft-power' switch. I don't take any responsibility for its correct operation or fitness of use for a particular purpose and any ensuing damage. Please use this at your own risk.
Thanks!