I'm guessing the errors occur during ModelSim simulation. That's a common problem if you haven't yet compiled the Xilinx simulation libraries (refer to the ISE "Synthesis and Simulation Design Guide"). Difficult to say for sure without knowing which software tools are involved.
dear thanks.yes those all are primitive.and now i have complied it and got just one warning.its ok.
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks