i am doing a project on designing an ic for controlling the speed of a dc motor . the main modules in my project are pwm ,encoder,counter and pid..
i have generated the codes for counter, pid and pwm seperately but when i try to link it ..i am not getting it right ...plz help me..
If it just how to connect between 3 modules, then..
you can create another module as a top module and connect all your modules(counter, pid etc...) inside this top module as what you said
i want to input the output of counter to pid and output of pid to pwm
Technically speaking you *should* TEST your individual modules first! And, by including them into a testbench file individually to make sure they work as expected in simulation, you will also learn how to connect them up in an upper level file to each other!
here i am adding the code for 3 modules counter,pid and pwm...plzz help me to link these three modules....in such a way that i want the output of counter to be given as the error signal input of pid(e_in) and the out put of pid (u_out) as the the input of pwm(switches)....plzz help....thanks in advance..
Code:
module count(clk,a,out,r,n,e);
input clk;
input a;
input [7:0]r;
input [7:0]n;
integer counter=0;
output reg [7:0]e;
output reg [7:0]out;
reg [7:0]temp;
always @ (a)
begin
if (a==1) counter=counter+1;
temp=(counter/r);
out=(temp*n);
if
(out>=200) e=out-200;
else
e=200-out;
end
endmodule
Code:
module PIDdddd(u_out,e_in,clk,reset,u);
output signed [15:0] u_out;
output signed [15:0] u;
input signed [15:0] e_in;
input clk;
input reset;
parameter k1=107;
parameter k2 = 104;
parameter k3 = 2;
reg signed [15:0] u_prev;
reg signed [15:0] e_prev1;
reg signed [15:0] e_prev2;
assign err=(e_in/5);
assign u =(u_prev)+(k1*err)+(k3*e_prev2);
assign u_out = u+(-(k2*e_prev1));
always @ (posedge clk)
if (reset == 1) begin
u_prev <= 0;
e_prev1 <= 0;
e_prev2 <= 0;
end
else begin
e_prev2 <= e_prev1;
e_prev1 <= err;
u_prev <= u_out;
end
endmodule