PLZ ... Help me !!! increment the address of SRAM

[Bebo]

Hi...
As I said before that I am a beginner in verilog and I have a problem in my code i don't know how to solve the problem..

my project is to save an image ( 142 X 185) in the SRAM
so i need 18 location for each pixel of the image

I tried to write a code that increment the address of SRAM with receiving byte.
and i want to display the address increments in the LED


this is my code :

############################################

module MEM_SRAM (
Data_Bus, // Data Bus
Address, // RAM Address
nRD, // RAM Read Enable
nWR, // RAM Write Enable
nCE, // RAM Chip Enable
nUB, // RAM Upper Byte
nLB, // RAM Lower Byte
Data_In,
LEDG,
WE); // Write Enable

output [17:0] Address; // RAM Signals
inout [7:0] Data_Bus;
output nRD, nWR;
output nUB, nLB;
output nCE;
input WE; // Write Enable
reg [16:0] Address_In = 17'h0 ;
input [7:0] Data_In;
output [17:0] LEDG;
assign nUB = 1'b1; // Disable Upper Byte
assign nLB = 1'b0; // Enable Lower Byte
assign nCE = 1'b0; // Enable Chip
assign nRD = 1'b0; // Read Enable
assign nWR = !WE; // Write Enable


always @ ( WE )
begin : SRAM_WRITE
Data_Bus = WE? Data_In : 8'hzz;
Address[17:0] = Address_In+1;
LEDG = Address_In;


end

endmodule


############################################

i found these errors :

Error (10137): Verilog HDL Procedural Assignment error at MEM_SRAM.v(39): object "Data_Bus" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at MEM_SRAM.v(40): object "Address" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at MEM_SRAM.v(41): object "LEDG" on left-hand side of assignment must have a variable data type

PlZ help me

 

[research_vlsi]

1. assignments inside always block should be declared as "reg"
2. inout variables should be declared with continuous assignment statements (assign)

try this

output reg [17:0] Address; // RAM Signals // include reg
inout [7:0] Data_Bus;

output nRD, nWR;
output nUB, nLB;
output nCE;
input WE; // Write Enable
reg [16:0] Address_In = 17'h0 ;
input [7:0] Data_In;

output reg [17:0] LEDG; // include reg

assign nUB = 1'b1; // Disable Upper Byte
assign nLB = 1'b0; // Enable Lower Byte
assign nCE = 1'b0; // Enable Chip
assign nRD = 1'b0; // Read Enable
assign nWR = !WE; // Write Enable


always@(WE)
begin

Address = Address_In + 1;
LEDG = Address_In;
end

assign Data_Bus = WE? Data_In : 8'hzz;

endmodule