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ethernet filtering -- eg, using the Xilinx TEMAC interface -- 8b per cycle + valid + delayed "end of packet" -- create a system that can detect ICMP traffic at a specific address. (use xilinx.com and wikipedia.com for details. use tcpdump/wireshark to get icmp packets for your simulations)
lvl 2 -- add logic for vlan capability
lvl 3 -- add a packet buffer and logic for responding to "ping".
practical, intermediate -- create a system that can decode IRIG-B (DC levels).
lvl 2 -- convert IRIG to UTC for a given year.
lvl 3 -- handle leap seconds correctly.
practical, advanced -- examine what happens when you take any state machine and try to achieve 400MHz+ performance in an FPGA. The issue is that state machines tend to have complex logic or control complex logic. When simple operations take 2+ cycles to complete, it makes the state machine very complex. Typically so complex that you look for alternative methods and implementations.