pls pls save me from this index value warning

[srikanth 123]

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:04:49 02/15/2013 
-- Design Name: 
-- Module Name:    ram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

package memory is 
type mem_data is array (23 downto 0) of bit_vector(7 downto 0);
end memory;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.memory.all;


entity ram is

port(
     add_bus:in std_logic_vector(31 downto 0);
	  data_bus1:in bit_vector(31 downto 0);
	  data_bus2,data_bus0:out bit_vector(31 downto 0);
	  mem_ctrl:in bit_vector(2 downto 0);
	  data_out:out std_logic_vector(31 downto 0);
	  clk:in std_logic
	  );
	  
end ram;

architecture Behavioral of ram is

begin
process(add_bus,data_bus1,mem_ctrl,clk)

variable i1,i2,i3:integer;
variable i:integer ;
variable ram_data:mem_data :=  (("00000000"),
									 ("00000000"),
									 ("00000000"),
									 ("00000100"),
									 ("00000000"),
									 ("00000000"),
									 ("00000000"),
									 ("01000000"),
									 ("00000000"),
									 ("00000000"),
									 ("00000000"),
									 ("00000010"),
									 ("00000000"),
									 ("00000000"),
									 ("00000000"),
									 ("00000001"),
									 ("00000000"),
									 ("00000000"),
									 ("00000000"),
									 ("10000000"),
									 ("01111110"),
									 ("01100100"),
									 ("01100000"),
									 ("00000000"));
begin
case add_bus is
 when "00000000000000000000000000000000" => i:= 0;
 when "00000000000000000000000000000001" => i:= 1;
 when "00000000000000000000000000000010" => i:= 2;
 when "00000000000000000000000000000011" => i:= 3;
 when "00000000000000000000000000000100" => i:= 4;
 when "00000000000000000000000000000101" => i:= 5;
 when "00000000000000000000000000000110" => i:= 6;
 when "00000000000000000000000000000111" => i:= 7;
 when "00000000000000000000000000001000" => i:= 8;
 when "00000000000000000000000000001001" => i:= 9;
 when "00000000000000000000000000001010" => i:= 10;
 when "00000000000000000000000000001011" => i:= 11;
 when "00000000000000000000000000001100" => i:= 12;
 when "00000000000000000000000000001101" => i:= 13;
 when "00000000000000000000000000001110" => i:= 14;
 when "00000000000000000000000000001111" => i:= 15;
 when "00000000000000000000000000010000" => i:= 16;
 when "00000000000000000000000000010001" => i:= 17;
 when "00000000000000000000000000010010" => i:= 18;
 when "00000000000000000000000000010011" => i:= 19;
 when "00000000000000000000000000010100" => i:= 20;
 when "00000000000000000000000000010101" => i:= 21;
 when "00000000000000000000000000010110" => i:= 22;
 when "00000000000000000000000000010111" => i:= 23;
 when others =>
 null;
 end case;
 i1:=i+1;
 i2:=i+2;
 i3:=i+3;
 
 if(clk'event and clk = '1') then
 if(i<= 20) then
 if (mem_ctrl(2) = '1') then
 --some = := (data_bus1(7 downto 0));
 ram_data(i) := (data_bus1(7 downto 0));
ram_data(i1) := (data_bus1(15 downto 8));
--ram_data(i1) := (data_bus1(15 downto 8));
ram_data(i2) := (data_bus1(23 downto 16));
 ram_data(i3) := (data_bus1(31 downto 24));
 data_out <=to_stdlogicvector(ram_data(i3)&ram_data(i2)&ram_data(i1)&ram_data(i));
-- wait for 0ns;
 end if;
 if (mem_ctrl(1) = '1') then
 --wait for 10ns;
 data_bus0 <= (ram_data(i3)&ram_data(i2)&ram_data(i1)&ram_data(i));
--wait for 0ns;
end if;
else 
null;
end if;
if(i<23) then
if (mem_ctrl(0) = '1') then
 --wait for 20ns;
 data_bus2 <= ("000000000000000000000000"&ram_data(i));
 --wait for 0ns;
 end if;
 end if;
if (i >20) then
null;
end if;
end if;
end process;
end Behavioral;

WARNING:Xst:790 - "C:/Xilinx/one/ww.vhd" line 121: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/one/ww.vhd" line 125: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/one/ww.vhd" line 128: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/one/ww.vhd" line 131: Index value(s) does not match array range, simulation mismatch.

 

[TrickyDicky]

i1, i2 and i3 are integers, so they have a 32 bit range. Because you havent constrained them, they are potentially bigger than the rams they are accessing.

 

[sureshaa]

Re: pls pls help me this is very urgent for my project

Hi Srikanth,

You just consider one condition:
when add_bus= 00000000000000000000000000010111, then i value will be 23.
Then obviously i1,i2,i3 values will be 24(They have been declared as variable.It will get update asap).
Then it will try to force ram_data(24) := (data_bus1(15 downto 8));but you have declared your memory as 0 to 23 only. Thats why it is showing these warnings.

 

[srikanth 123]

Re: pls pls help me this is very urgent for my project

thank you for your reply suresh i didnot get the explanation you did...i am sry to ask but can you just edit this code and send me pls dont mind it...

 

[srikanth 123]

thank you sir trickydicky,i didnot get the explanation sir,,,can you pls edit for me the code...sry sir for asking me....

 

[mrflibble]

thank you sir trickydicky,i didnot get the explanation sir,,,can you pls edit for me the code...sry sir for asking me....

Soooo you don't understand it, but want someone else to fix your code for you. Because that way you will be able to fix your next problem .... how exactly? Maybe I am missing something, which is why I ask how you think this educational process works.

What TrickyDicky means is that the integers you use do not match the bus width of your RAM. So you have to change your code so that it does match...

I am not sure what the politically correct VHDL way of doing things in a testbench is, but I suspect you will want to use a proper data type (of the correct bit width) for your address instead of a (32 bit) integer.

 

[srikanth 123]

i am sry everyone for asking to correct the code...i mean it...still this warning has not gone even if i changed i value to bit_vector(3 downto 0)

 

[sureshaa]

Re: pls pls help me this is very urgent for my project

You have declared the 'i,i1..' in integer. So convert that first into vector. And control the i values at max of "0 downto 23".This warnings wont come.

In Last thread I have mistakenly gave the no as 24. In your case it will come for 16777216(2^24) th count.

 

[TrickyDicky]

you dont need to convert i1,2,3 to vectors - that just makes life annoying.
You just need to constrain them when you declare them:

signal i1 : integer range 0 to 32; --constrained to 5 bits when implemented.