Plot of NMOS gate capacitance vs applied voltage ??

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cmos_ajay

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Attached is a curve of NMOS gate capacitance vs applied gate voltage.
Can someone show a test circuit diagram to obtain this curve using any SPICE simulator ?
 

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See here:

Use a swept DC source between GND and gate:

Similar for NMOS
 
Last edited:

I would use a transient ramp, not sure a DC analysis
(static or swept) will give you the capacitances'
effects.

Keep gate current and take I, dV/dt in Calculator,
plot I/(dV/dt) against V on the X-axis (change axis
properties in the viewer).
 

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