MAHSA88
Newbie level 1
Hi,
I am attempting to simulate the PLL phase noise in ADS using the available PLL blocks which I have implemented in transistor level in ADS. However, the closed loop analysis in ADS does not worked so I wanna do by adding the noise of each block to the s-domain PLL model but I don't know how?
Is there anyone help me with this problem?
Thanks,
I am attempting to simulate the PLL phase noise in ADS using the available PLL blocks which I have implemented in transistor level in ADS. However, the closed loop analysis in ADS does not worked so I wanna do by adding the noise of each block to the s-domain PLL model but I don't know how?
Is there anyone help me with this problem?
Thanks,