Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PLL phase noise analysis in ADS

Status
Not open for further replies.
M

MAHSA88

Newbie level 1
Joined
Dec 24, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
9
Hi,
I am attempting to simulate the PLL phase noise in ADS using the available PLL blocks which I have implemented in transistor level in ADS. However, the closed loop analysis in ADS does not worked so I wanna do by adding the noise of each block to the s-domain PLL model but I don't know how?
Is there anyone help me with this problem?
Thanks,
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top