PLL hard macro placement

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biju4u90

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Generally, we place hard macros at the periphery of the chip to avoid congestion in the middle of the chip. What about the PLL hard macro?? Since PLL acts as a clock source, it will be routing to many points. In such a scenario, will it be intelligent to place the PLL macro at the centre of the chip??
 

You could, but it is not necessarily better. You would have to route the source clock from the pad to the center of the chip, and that is not desirable.
 
Can you explain why it is not desirable??
 

You would have to route the source clock from the pad to the center of the chip, and that is not desirable.
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Think about the net delay.
If you can place your design near the PLL and that would reduce clock net delay significantly.

Whereas if your PLL is somewhere at the center of the chip, and say you place your logic also at the center, then how would you tackle the IO net delays (definitely a chip will have lots of IOs)?
You have to connect you top level design ports to the chip pins.
 

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