firasgany7
Junior Member level 1
Hello guys,
I have a PLL design in VerilogA, and I did an 'ams' simulation in cadence that shows that the PLL reaches locking state within 4us]:
how do I plot the Phase margin and Gain of PLL? i'm trying to do an ac simulation but got confused what to put at the inputs and what signals should I picked to draw the plot.
when I tried to pick vout/fdiv or vout/fref I got a constant frequency. I couldn't explain the result.
I have 30Mhz reference clock with N=64 dividing ratio, and locking frequency: 1.9Ghz.
these are the options that I see in the ADE simulation analysis:
thanks,
firas
I have a PLL design in VerilogA, and I did an 'ams' simulation in cadence that shows that the PLL reaches locking state within 4us]:
how do I plot the Phase margin and Gain of PLL? i'm trying to do an ac simulation but got confused what to put at the inputs and what signals should I picked to draw the plot.
when I tried to pick vout/fdiv or vout/fref I got a constant frequency. I couldn't explain the result.
I have 30Mhz reference clock with N=64 dividing ratio, and locking frequency: 1.9Ghz.
these are the options that I see in the ADE simulation analysis:
thanks,
firas