Hi,
how do I check if they are linearized around a stable operating point? and why reaching a locking state is not equivalent to reaching this point? can you please what does this operation point mean in terms of PLL component output signals?
and no I don't break the loop, I'm trying first to calculate the closed loop gain, but also open loop is on the list.
my problem is that I don't know how to technically apply this in Cadence (on transistor level amplifiers for example I know how to do it, there are alot Youtube videos that explain how to calculate Phase and Gain Margin, but since this simulation involves VerilogA 'ams simulation' , it is something new for me ).