supply insensitive pll design
Hope that this can give a clearer picture and advice from you guys.
Initially my PLL can lock to the reference clock (160MHz) using PFD and weaker Charge Pump. After lock to reference clock, the PLL switch to the Phase Detector and stronger Charge Pump. During this time, some mismatch in the input data, cause the PLL to increase its frequency until it is clamped by VCO max operating limit, 250MHz (which is VCO supply voltage). When switch back to the PFD circuit when VCO operate at 250MHz, it is only able to lock back after a long period.
Do you guys have any idea of which circuit which may potentially cause this to happen. Thanks.