kurukuru said:
However the manual suggests that VHDL user can create Verilog wrapper to cover VHDL code before import to system. Can anyone please give me an example of Verilog wrapper code?
Hi
both *.vhd and *.v files are in attachment.
Below code is Verilog wrapper to cover VHDL code of simple up counter
// VerilogWraper_upcounter_vhd.v
`timescale 1ns/100ps
module VerilogWraper_upcounter_vhd
(
input wire extClk,
input wire pbRstN, // active low reset input
input wire Enable,
output wire [07:00] Count
);
up_counter Instance_0
(
.cout ( Count ), // output [07:00]
.enable ( Enable ), // input
.clk ( extClk ), // input
.reset ( ~pbRstN ) // input active high reset
);
endmodule
Below code is up_counter.vhd. This code is taken form asic-world web site just to give you an example.
-------------------------------------------------------
-- Design Name : up_counter
-- File Name : up_counter.vhd
-- Function : Up counter
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity up_counter is
port (
cout
ut std_logic_vector (7 downto 0); -- Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;
architecture rtl of up_counter is
signal count :std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= count + 1;
end if;
end if;
end process;
cout <= count;
end architecture;
HTH
--
Shitansh Vaghela