You're basically correct!
using a several 100 MHz clock frequency, a considerable resolution could be achieved, at least within the digital circuit. Actually I didn't say, this would be impossible, I said 1st it won't be used in practice and 2nd you won't find a commercial device. In my view, dual-slope as a dominant technique for slow ADC has been almost replaced by sigma-delta. Don't want to analyze this in detail, but you probably could confirm this as an observation.
There are some basic properties, that generally limit dual slope accuracy. Integration capacitor loss factor is one, but only slightly depending on ADC speed. Much more speed dependant is nonideal comparator behaviour. It may be difficult to achieve 12 bit accuracy in analog circuit part at the said speed. I guess, that no designer has actually tried during the last 10 or even 20 years, cause other ADC operation principles most likely are promising more benefit.
But I'm not a IC designer and have no need to decide anything in this field. As an analog designer using ADC, I can say, I didn't start a new design with a dual slope for the last 10 years.
Regards,
Frank