Hello All,
I am engineering student i want write a code in vhdl go get the simulations as per the picture attached and tried doing that but not getting please help me with the code.
thankyou,
Code VHDL - [expand ] 1
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library IEEE ;
use IEEE .STD_LOGIC_1164 .ALL ;
use IEEE .STD_LOGIC_UNSIGNED.ALL ;
use IEEE .NUMERIC_STD .ALL ;
entity DLR2416 is
Port ( CLK : in std_logic ;
reset : in std_logic ;
enable : in std_logic ;
WRbar : out STD_LOGIC ;
CEbar : out STD_LOGIC ;
CLRbar : out STD_LOGIC ;
A0A1 : inout STD_LOGIC_vector ( 1 downto 0 ) ;
data : out STD_LOGIC_VECTOR ( 6 downto 0 ) ) ;
end DLR2416;
architecture Behavioral of DLR2416 is
constant Lu_t : std_logic_vector ( 6 downto 0 ) := "0000001" ;
constant Lu_a : std_logic_vector ( 6 downto 0 ) := "1001111" ;
constant Lu_c : std_logic_vector ( 6 downto 0 ) := "0000110" ;
constant Lu_d : std_logic_vector ( 6 downto 0 ) := "0000000" ;
constant Lu_f : std_logic_vector ( 6 downto 0 ) := "1111111" ;
signal I : STD_LOGIC_vector ( 1 downto 0 ) ;
--signal temp :STD_LOGIC_vector(1 downto 0);
begin
process ( CLK,reset,enable,I)
variable COUNT : integer ;
begin
if ( CLK'Event and CLK = '1 ' and enable = '1 ') then
if ( reset = '0 ') then
if ( count = 0 ) then
CEbar <= '1 ';
CLRbar <= '0 ';
A0A1 <= I;
--WRbar <= '1';
end if ;
if ( count = 1 ) then
CEbar <= '0 ';
CLRbar <= '1 ';
A0A1 <= I;
--WRbar <= '1';
end if ;
if ( count < 10 ) then
CEbar <= '0 ';
CLRbar <= '1 ';
A0A1 <= I;
--WRbar <= '1';
end if ;
if ( count <= 90 ) then
CEbar <= '0 ';
CLRbar <= '1 ';
A0A1 <= I;
--WRbar <= '0';
case A0A1 is
when "00" => data <= Lu_t;
when "01" => data <= Lu_a;
when "10" => data <= Lu_c;
when "11" => data <= Lu_f;
when others => data <= Lu_d;
end case ;
end if ;
if ( count <= 140 ) then
CEbar <= '0 ';
CLRbar <= '1 ';
A0A1 <= I;
--WRbar <= '1';
end if ;
COUNT <= COUNT + '1 ';
--elsif(reset = '1')then
else
CLRbar <= '0 ';
count := 0 ;
CEbar <= '1 ';
A0A1 <= I;
WRbar <= '1 ';
end if ;
--end if;
end if ;
end process ;
end Behavioral;
Last edited by a moderator: Nov 26, 2015