Please help.... method to connect an output in a VHDL module

[LF_LF]

Hey,everybody.
I am constructing an VHDL code for clock divider and specification of 2 pins.
I need to trigger 2 pins using DE2 board for 1 clock cycle(auto trigger down itself after 1 clock cycle).
However, i have no idea how to convert that output of my clock divider for the clock of my pin specification. Can anyone please help me?

My clock divider convert 27MHz to 500KHz and i need to trigger these 2 pins(buttons from DE2 board) using 500kHz.
My code for the pin specification are:

process(clkin) --- i think my problem is here!!!
begin
if A0 = '1' and (rising_edge(clkin)) then
A0_out <= '1';
count1 := '1';
if count1='1' and (rising_edge(clkin)) then
A0_out<= '0';
count1 := '0';
end if;
end if;
end process;

process(clkin)
begin
if convst = '1' and (rising_edge(clkin)) then
convst_out <= '1';
count2 := '1';
if count2='1' and (rising_edge(clkin)) then
convst_out<= '0';
count2 := '0';
end if;
end if;
end process;

 

[bapodradhairyab]

where you want to use the clock???
If you are using any FPGA use DCM(xillinx) or PLL(others) for this kind of division, ready core will be there for division
.....
because you are not going to get exact 500k by division.

 

[LF_LF]

Re: Please help.... method to connect an output in a VHDL mo

I need to synchronizes the clock of my DE2 board(altera) from 27MHz to my ADC (ADS7861 - 500Khz). As i need to verify the ADC, therefore i have been asked to constructed a VHDL code in DE2 board and connect to ADC for testing. According the datasheet of ADC, two inputs need to trigger for 1 clock cycle only, therefore i tried to construct code to make it trigger back after 1 clock cycle itself.

As it is my first time use the DE2 board, i have no idea what function it has for that board(of course i know the chips and their functions according to user manual).
I have no idea about the PLL and DCM.Can anyone briefly explain the procedures or may anyone show my any link or documentation?

 

[FvM]

The problem is very unclear. You don't say, where the ADC input clock comes from, why you intend to use the 27 MHz
FPGA clock and on which ADC signal you wan to synchronize.

I guess, the problem is reading the ADC serial data, it has to be performed at 8 MHz bit clock.

For writing VHDL code, please refer to basic structure rules in literature or e.g. Altera Q.uartus VHDL templates. Nested
rising_edge() expressions surely won't result in what you are trying to achieve.

 

[LF_LF]

Re: Please help.... method to connect an output in a VHDL mo

Well,my ADC input clock is come from Altera DE2 board. The Altera DE2 board has 3 clock input, which are 27MHz, 50Mhz and SMA external clock input. Therefore i use 27MHz.(well i didn't choose external clock input is due to complexity of building another clock generator)

The ADC is specified to have 500Khz according to datasheet. Therefore i tried to synchronize or convert 27MHz to 500 Khz.

Well, about the 8Mhz you mentioned about, it stated it is external clock, optinal 8Mhz but according to pin description, it state this clock pin control the sampling rate by equation Clock = 16 * f(sample).... well, i guese the 16* (500kHz) = 8MHz.
Then is that i misunderstood that i need to supply 8 Mhz to ADC at the clock pin instead of 500Khz? Sorry, i am a bit confused.

About the code, i think i need to refer back as i am just a newbie to this language programing.

 

[FvM]

If you want to achieve 500 kS/s rate, you have to supply 8 MHz to the ADC. It's most easy to run the ADC data receiption
at 8 MHz or a multiple of it (e.g. 16 or 32 MHz), depends on which clocks are used in your FPGA design. To generate exactly
this frequency, you have to use a PLL MegaFunction.

 

[LF_LF]

Re: Please help.... method to connect an output in a VHDL mo

Thanks for FvM.

For the clock . i know how to pass the output of clock cycle to next process already.(I read the MegaFubction PLL and i will try it later)

However, i am facing the trigger problem. I tried to use counter to trigger it 0 after 1 clock cycle, but it doesn't work (even i can stimulate it successfully for VHDL code but it show constant to 1 without trigger back to 0 in the waveform stimulation )

My code are:
+++ above are the clock divider codes which are in the same architecture

process(clk)
begin
if reset = '1' then
A0_out <= '0';
A1_out <= '0';

elsif(rising_edge(mux) and A0 = '1') then
count1 <= count1 +1;
A0_out <= '1';
if count1 > 1 then
A0_out <='0';
count1 <= 0;
end if;

elsif(rising_edge(mux) and A1='1') then
count2 <= count2 +1;
count2 <= count2 +1;
A1_out <= '1';
if count2 > 1 then
A1_out <='0';
count2 <= 0;
end if;

end if;
end process;

 

[FvM]

I fear, you have to go several steps back and learn, how VHDL works. It's a hardware description language,
different from a procedural programming language as C. A signal assignment e.g. gets effective after the current clock edge.

It may be easier to think of the required logic as a hardware circuit and construct it from logic gates, flip flops, counters
and shift registers.

 

[oliverlin09]

Re: Please help.... method to connect an output in a VHDL mo

process(clk)

You have a reset signal.
use "process(clk, reset)" may be better.

elsif(rising_edge(mux) and A0 = '1') then

The correct way to write it is:
elsif (clk'event and clk = '1') then

and some bits in your VHDL programme need to be changed as well.

 

[LF_LF]

Re: Please help.... method to connect an output in a VHDL mo

Thanks to all.
I have create again since the last 1 cant be used
I got the waveform this time. However, regarding the counter of convst, i face some problem. I need to generate pulses every 16 clock cycles, but it show me 17 clock cycles.
Can someone help me take a look for this. I have tried the number of clock cycles that i specified (by trial and error). It also show the wrong waveform



LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
LIBRARY work;

entity siggen is
port(
clkin: in std_logic;
reset: in std_logic;
convst: out std_logic;
A0 : out std_logic
);
end siggen;

architecture fpga of siggen is

signal count1: integer range 0 to 2;
signal count2: integer range 0 to 15;

begin
process(clkin)
begin
if reset ='1' then
convst <= '0';
count1 <= 0;
A0 <= '0';
count2 <= 0;

elsif rising_edge(clkin) then
if count1 <1 then
convst <='1';
count1 <= count1 +1;
else convst <='0';
A0 <= '1';
count2 <= count2 +1;
if count2 = 15 then
count1 <= 0;
count2 <= 0;
end if;

end if;
end if;

end process;

end fpga;

 

[FvM]

Re: Please help.... method to connect an output in a VHDL mo

You're counting 17 states, 1 state for count1 = 0 and 16 states for count2 = 0..15.

I don't see the purpose of using two counters. Just have one (counting 0..15) and derive all actions from it's value. You may
want to use case constructs or if statements, as you like. As a debugging hint: You can display internal signals (e.g. counter
values) in the simulator. You also can use Q.uartus SignalTap II to perform hardware debugging of your circuit.
Particularly interesting, when interfacing a real ADC.

P.S.: I see that you are running the timing simulation at 100 MHz. You should better use 8 MHz as required by the chip
and also pay attention to the required setup and hold times. It's recommended to set CONVST at the falling rather than the
rising input clock edge.

 

[LF_LF]

Re: Please help.... method to connect an output in a VHDL mo

Thank you FvM.
For the 100Mhz, i just simply used for testing purpose.
For the 8MHz, it is 16 * 500kHz. However, the circuit before the ADC (Connection : motor -- current transducer -- instrumentation amp -- ADC -- DE2) is 50Hz. For that calculation, is it i need to take care of curcuit before which has 50 Hz (f sample)? If using 50Hz, it is 800Hz only.

From the diag, it seen like the convst is trigger at falling_edge even i wrote rising_edge in my code. Is it due to clock delay? Is that any method/ feature in Q'tus can eliminate delay?

Hm, one more. Can someone provide me the steps to interconnect 2 blocks from different VHDL file? I know how to create an block according to online user tut but it didn't let me know how can i input the block that has been saved in different file. I tried copy the block and paste it but it cant locate the file when i want to open the code from block. (i also tried to browse from the " insert symbol by double click on the schematic but it also cant locate the file)

Thank you in advanced.

 

[FvM]

Re: Please help.... method to connect an output in a VHDL mo

Regarding sampling rates, if the input signal is 50 Hz (most likely AC), you may want to sample it at a considerable higher rate
to e.g. calculate RMS, harmonics, whatsover. That's a different topic not directly related to basic ADC FPGA interface code,
I think. If you only need 50 Hz (or possibly 1 kHz) sampling rate, you would use a different ADC type.

Yes, there's an about 5 ns clock to output delay with standard FPGA. However, if you source the ADC CLK and CONVST from
FPGA, the relative delay is smaller. At a rather small clock frequency of 8 MHz, the timing should work utilizing systematic
FPGA behaviour, without delay adjustment. Selecting rising or falling clock edge is most likely sufficient.

Working with components and instances is a topic of VHDL text books, there's a lot out there.