Re: Please help.... method to connect an output in a VHDL mo
Regarding sampling rates, if the input signal is 50 Hz (most likely AC), you may want to sample it at a considerable higher rate
to e.g. calculate RMS, harmonics, whatsover. That's a different topic not directly related to basic ADC FPGA interface code,
I think. If you only need 50 Hz (or possibly 1 kHz) sampling rate, you would use a different ADC type.
Yes, there's an about 5 ns clock to output delay with standard FPGA. However, if you source the ADC CLK and CONVST from
FPGA, the relative delay is smaller. At a rather small clock frequency of 8 MHz, the timing should work utilizing systematic
FPGA behaviour, without delay adjustment. Selecting rising or falling clock edge is most likely sufficient.
Working with components and instances is a topic of VHDL text books, there's a lot out there.