May 17, 2009 #1 D DoraSzasz Junior Member level 1 Joined May 17, 2009 Messages 18 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,459 Hi,everyone! Can you tell me, please,how to make the following task: an BCD counter on 8 bits, using 74163 counters and logic gates. Can you tell me the code or some ideas? Thank you!
Hi,everyone! Can you tell me, please,how to make the following task: an BCD counter on 8 bits, using 74163 counters and logic gates. Can you tell me the code or some ideas? Thank you!
May 18, 2009 #2 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 Here is verilog code for 8 bit BCD counter Code: module bcd_counter (clk, rst_n, count); input clk, rst_n; output [7:0] count; reg [7:0] count; always @(posedge clk or negedge rst_n) if (!rst_n) count <= 8'h00; else if (count[3:0] == 9) begin count[3:0] <= 0; if (count[7:4] == 9) count[7:4] <= 0; else count[7:4] <= count[7:4] + 1; end else begin count[3:0] <= count[3:0] + 1; end endmodule // bcd_counter
Here is verilog code for 8 bit BCD counter Code: module bcd_counter (clk, rst_n, count); input clk, rst_n; output [7:0] count; reg [7:0] count; always @(posedge clk or negedge rst_n) if (!rst_n) count <= 8'h00; else if (count[3:0] == 9) begin count[3:0] <= 0; if (count[7:4] == 9) count[7:4] <= 0; else count[7:4] <= count[7:4] + 1; end else begin count[3:0] <= count[3:0] + 1; end endmodule // bcd_counter
May 18, 2009 #3 D DoraSzasz Junior Member level 1 Joined May 17, 2009 Messages 18 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,459 Thank you, nand_gates! This is the implementation with logic gates? Can you,please, comment a little bit, what you did there? Thank you a lot! Teodora
Thank you, nand_gates! This is the implementation with logic gates? Can you,please, comment a little bit, what you did there? Thank you a lot! Teodora