eunsicksea
Newbie level 1
![K-1.jpg K-1.jpg](https://www.edaboard.com/data/attachments/26/26149-343e70594b10dcfa52060b3a8f05de7e.jpg)
hi... i have big problem...
i have to design a sci based n-stage cmos ring oscillator.
Each inverter may have the same size of W/L. target duty ratio of Vx = 50% +/- 1% ring Ring oscillator output frequency f = 1 GHz when Vctrl=0V.
Trise/Tfall of Vx, Vy, Vz, & Vzb < 100ps
so i have tried to design oscillator...
but i dont know how to do that...
please help me...
just in oscillator let me know what to do...