What are you trying to achieve? If you want to control the ADC, you have to design a SPI master interface. A VHDL code for the slave would be needed only to simulate the slave's behaviour.I have constructed the VHDL code for master(FPGA) and slave (ADC).
You are talking in riddles...For the code, i found out some errors in master and slave(i think is the same error for both) and i failed to fix it after many trial.
valid VHDL syntax would be elseif ... thenelse(serial_data_clock'event = '1' and serial_data_clock ='1') then
process (clk,reset)
begin
if reset = '1' then
-- reset action
elsif rising_edge(clk) then
-- action on each clock edge
if condition1 then
-- conditional action
end if;
end if;
end process;
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