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| LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fft_test IS
END fft_test;
ARCHITECTURE behavior OF fft_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fft1
PORT(
clk : IN std_logic;
nfft : IN std_logic_vector(4 downto 0);
nfft_we : IN std_logic;
start : IN std_logic;
xn_re : IN std_logic_vector(7 downto 0);
xn_im : IN std_logic_vector(7 downto 0);
fwd_inv : IN std_logic;
fwd_inv_we : IN std_logic;
rfd : OUT std_logic;
xn_index : OUT std_logic_vector(9 downto 0);
busy : OUT std_logic;
edone : OUT std_logic;
done : OUT std_logic;
dv : OUT std_logic;
xk_index : OUT std_logic_vector(9 downto 0);
xk_re : OUT std_logic_vector(7 downto 0);
xk_im : OUT std_logic_vector(7 downto 0);
blk_exp : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal nfft : std_logic_vector(4 downto 0) := (others => '0');
signal nfft_we : std_logic := '0';
signal start : std_logic := '0';
signal xn_re : std_logic_vector(7 downto 0) := (others => '0');
signal xn_im : std_logic_vector(7 downto 0) := (others => '0');
signal fwd_inv : std_logic := '0';
signal fwd_inv_we : std_logic := '0';
--Outputs
signal rfd : std_logic;
signal xn_index : std_logic_vector(9 downto 0);
signal busy : std_logic;
signal edone : std_logic;
signal done : std_logic;
signal dv : std_logic;
signal xk_index : std_logic_vector(9 downto 0);
signal xk_re : std_logic_vector(7 downto 0);
signal xk_im : std_logic_vector(7 downto 0);
signal blk_exp : std_logic_vector(4 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fft1 PORT MAP (
clk => clk,
nfft => nfft,
nfft_we => nfft_we,
start => start,
xn_re => xn_re,
xn_im => xn_im,
fwd_inv => fwd_inv,
fwd_inv_we => fwd_inv_we,
rfd => rfd,
xn_index => xn_index,
busy => busy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im,
blk_exp => blk_exp
);
clk<= not clk after 50ns;
process(clk)
file f : text;
constant filename : string :="input.txt";
variable L : string;
variable i : integer:=0;
variable b : std_logic_vector(7 downto 0);
begin
file_open(input,read_mode);
if((i<=256) and (not endfile(f))) then
readline(f,l);
read (f,l,conv_integer(b));
xn_re<=b;
i:=i+1;
end if;
end process;
nfft<="00110";
nfft_we<='1';
start<='1';
fwd_inv<='1';
fwd_inv_we<='1';
END; |