hayoula
Member level 1
Hi,
I have a circuit which uses latch-based clock-gating and clock-selection logic:
- Using a control signal I select a clock or its inverted for a register.
- Register is negative edge-triggered and I have added an latch-based clock-gating using DC (You can see the clock-gating logic).
As you can see one signal goes to both main (last) OR gate and the latch as the clock. But different path is considered for each one and it violates the clock-gating hold-time. But circumstances in my circuit are so that it is impossible that this situation occurs. How can I say DC to ignore this situation?
Please help.
Thanks in advance
I have a circuit which uses latch-based clock-gating and clock-selection logic:
- Using a control signal I select a clock or its inverted for a register.
- Register is negative edge-triggered and I have added an latch-based clock-gating using DC (You can see the clock-gating logic).
As you can see one signal goes to both main (last) OR gate and the latch as the clock. But different path is considered for each one and it violates the clock-gating hold-time. But circumstances in my circuit are so that it is impossible that this situation occurs. How can I say DC to ignore this situation?
Please help.
Thanks in advance