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please give me one project idea..

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nee_naresh04

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multihdl

hai..i am doing my post graduation..now i am entering into THESIS..so please give some project ideas ..provide some information plz..my area of interest is

ASIC Design--vhdl

FPGA Implimentation---vhdl
 

avimit

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What University are you with? What tools/resources you have.
 

nee_naresh04

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simulation tools for VHDL are ...MODELSIM,MULTIHDL..
SYNTHESIS TOOLS ..XILINX ISE WEBPACK, LENARDO SPECTURM..
LAYOUT TOOLS ..LASI,WINSPICE,ORCAD,MATLAB,MAGIC..

PLEASE GIVE SOME PROJECT IDEA FOR MY THESIS..THE TOOLS AVAILABLE TO ME R LISTED ABOVE..
 

sree205

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You could try out a project like 5-stage MIPS processor. Its a good start up project which can be a thesis too. Introductory books for these are available in the forum.
 

hezhengrong

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can you make your problem more clear !

for the implementation you can use the DesignCompiler & BlastCreate to synthesis your code, also you can use the BlastFusion & PhysicalCompiler to do the layout. For the simulation ModelSim and NCsim are very good tools.


regards
 

spauls

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You can do project in Signal Integrity it is good field right now.
 

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