always @(negedge clock)
begin
shift[posi]= datain;
posi<=posi+1;
if (posi==3'd0)
begin
if (shift[0]==0)
begin
dir0<=shift[1];
data0<=shift[2:7];
end
else
begin
dir1<=shift[1];
data1<=shift[2:7];
end
end
end
is this part:
dir0<=shift[1];
data0<=shift[2:7];
good if I want to have dir0 the value of the 2nd bit of shift,
and data0 the value of the last 5 bits of shift?
Yes, it's good, but dir0 will be the 2nd bit of shift and data0 will be last 5 bits of shift only when posi =0 and shift(0)=0... If this is your expected result, you're ok!