PLD Internal connections - attribute pin_numbers

[ZainZeus]

attribute pin_numbers

hi
Im new in this forum, so hello everyone and whatever, anyways straight to my question

I'm moreless new in VHDL programming and I wrote this code

library ieee;
use ieee.std_logic_1164.all;

entity maquina_contador is	
	port(
	Clk, Rst: in std_logic;
	SSE: in std_logic_vector(1 downto 0);
	OP: out std_logic_vector(1 downto 0)
	);
ATTRIBUTE PART_NAME OF maquina_contador: ENTITY IS "PALC22V10D";
ATTRIBUTE PIN_NUMBERS OF maquina_contador: ENTITY IS
   "clk:1 "&
   "rst:2 "&
   "sse(0):3 "&
   "sse(1):4 "&
   "op(0):22 "&
   "op(1):21 ";
end maquina_contador;

architecture maquina_contador of maquina_contador is   
type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12);
signal edo_presente, edo_futuro: estados;
begin
	process(SSE, edo_presente)
	begin
		case edo_presente is
			when s0 => op<="00";
			    if(SSE="00") then
				    edo_futuro<=s1;
			    elsif(SSE="01") then
				    edo_futuro<=s2;
			    elsif(SSE="10") then
				    edo_futuro<=s4;
			    else
				    edo_futuro<=s3;
			    end if;
			when s1 => op<="00";
			    if(SSE="10") then
				    edo_futuro<=s9;
				elsif(SSE="01") then
				    edo_futuro<=s5;
				else
					edo_futuro<=s1;
				end if;
			when s2 => op<="00";
			    if(SSE="00") then
				    edo_futuro<=s10;
				elsif(SSE="11") then
					edo_futuro<=s6;
				else
					edo_futuro<=s2;
				end if;
			when s3 => op<="00";
			    if(SSE="01") then 
				    edo_futuro<=s11;
				elsif(SSE="10") then
					edo_futuro<=s7;
				else
					edo_futuro<=s3;
				end if;
			when s4 => 
			    if(SSE="11") then
					edo_futuro<=s12;
				elsif(SSE="00") then
					edo_futuro<=s8;
				else
					edo_futuro<=s4;
				end if;
				op<="00";
			when s5 => op<="11";
			    edo_futuro<=s2;
			when s6 => op<="11";
			    edo_futuro<=s3;
			when s7 => op<="11";
			    edo_futuro<=s4;
			when s8 => op<="11";
			    edo_futuro<=s1;
			when s9 => op<="10";
			    edo_futuro<=s4;
			when s10 => op<="10";
			    edo_futuro<=s1;	 
			when s11 => op<="10";
			    edo_futuro<=s2;
			when others => op<="10";
			    edo_futuro<=s3;
			end case; 
		end process;
			
process(Clk, Rst)
begin
	if(Rst='1') then
		edo_presente<=s0;
	elsif(Clk'event and Clk='1') then
		edo_presente<=edo_futuro;
	end if;
end process;
end maquina_contador;

and you see the problem is when I try to compile this for some gal22v10 device, it not only gives me the inputs and outputs I specified but also it gives me some other that i didn't, it's shown on the galaxy report file:

                                 C22V10
                 __________________________________________
              clk =| 1|                                  |24|* not used       
              rst =| 2|                                  |23|= (edo_present.. 
         sse(0) =| 3|                                  |22|= op(0)          
         sse(1) =| 4|                                  |21|= op(1)          
       not used *| 5|                                  |20|* not used       
       not used *| 6|                                  |19|* not used       
       not used *| 7|                                  |18|* not used       
       not used *| 8|                                  |17|* not used       
       not used *| 9|                                  |16|= (edo_present.. 
       not used *|10|                                  |15|= (edo_present.. 
       not used *|11|                                  |14|= (edo_present.. 
       not used *|12|                                  |13|* not used       
                 __________________________________________

I didn't specified the output for the ones called: (edo_present... they are actual signals on my program.

So my guess is that if i label some variable as "signal" in my program, this device at least, will have to take those to some output pin. am I right? or is there anyway to avoid those signals to appear on the output pins?

I've only programmed vhdl code on fpga training boards so I wouldn't know for sure.

I'll apreciate any answer, thanks.
Have a nice day!

ZZ