What you describe describes high speed layouts with FPGA's CPLD's DDR memory, I do quite a few every year and have been doing these sort of designs for over a decade now. Do the best you can but don't get over worried about the inter plane capacitance, I often do boards with numerous power islands (separated by either a ferrite or an LDO), I try to place the capacitors as best as I can constrained by the design, but you must remember ALL PCB design is a compromise, otherwise we would never get boards out of the door, so aim for the best, but don't worry to much about the very finite details. When I do have to worry about power to such an extent, it is time to use power delivery system simulation software.
I don't know what system you use for layout, but all the main ones do have PDS simulation add ons, it may be worth you investigating this software, it is quite interesting to use and see the results for actual boards, though it may shock you:grin:
Another thing worth looking at is how you can achieve higher interplane capacitance with HDI PCB design, which I think gives the best usage of space and the best ELECTRICAL environment for signals.