Place and Route and Timing Analysis for XILINX

[syedshan]

Dear all,

I am now to have the Timing analysis for my design along with place and Route using Xilinx ISE.

Since I am learning I have few problems in understanding few things.

1- What input Jitter time should I place for my clock. How can I know what jitter time my clock has...?
2- Also can I save this same time constraints changing the syntax to .xcf and utilize it in synthesis ?


Regards and Many thanks in Advance
Shan.

 

[guitarguy12387]

Dear all,

I am now to have the Timing analysis for my design along with place and Route using Xilinx ISE.

Since I am learning I have few problems in understanding few things.

1- What input Jitter time should I place for my clock. How can I know what jitter time my clock has...?
2- Also can I save this same time constraints changing the syntax to .xcf and utilize it in synthesis ?


Regards and Many thanks in Advance
Shan.

Well I am by no means a timing expert, but as far as I remember, there's basically two different jitter specs for xilinx timing analysis: system jitter and input jitter. The former is system level and the latter you can get from your oscillator spec. Both are different types of constraints, I believe. Have a look in the timing constraints users guide for more info.

I'm not sure what exactly you mean for your second question

 

[manojkhandelwal]

Hi,
1. as far as i know, we dont place any constraint like clock jitter .........the tool itself calculates it and shows them in static timing report.
2. also the timing constraints you apply for synthesis are forward annotated to the backend of your tool (P& R).

Thanks,
Manoj