PISO Shift Register (Verilog-A)

[yahzee]

Hey guys, I'm very new to Verilog-A, and there doesn't seem to be a lot of information about Verilog-A online besides the LRM. There's lots of info about Verilog, Verilog-AMS, VHDL and other related languages but nothing that really pertains to Verilog-A. I am trying to code a 10 bit parallel in, serial out shift register and I'm running into trouble of exactly how to output serially. I believe that I have the parallel inputs correctly but I could be wrong, so any help is really appreciated. One of my thought processes is that I could have another clock that was multiplied by 10, in order to shift out each bit at the correct time. Basically I do not know how to move forward from the code here:

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Code Verilog - [expand]
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module test
   (vin_d0,vin_d1,vin_d2,vin_d3,vin_d4,vin_d5,vin_d6,vin_d7,vin_d8,vin_d9
   ,vout_d,vclk);
input vin_d0, vin_d1,vin_d2,vin_d3,vin_d4,vin_d5,vin_d6,vin_d7,vin_d8,vin_d9;   
electrical vin_d0,vin_d1,vin_d2,vin_d3,vin_d4,vin_d5,vin_d6,vin_d7,vin_d8,vin_d9;
output vout_d;
electrical vout_d;
electrical vclk;
 
 
   parameter real vlogic_high = 5;
   parameter real vlogic_low = 0;
   parameter real vtrans = 2.5;
   parameter real tdel = 3u from [0:inf);
   parameter real trise = 1u from (0:inf);
   parameter real tfall = 1u from (0:inf);
   
   integer i;
   integer d[0:9];
 
   analog begin
      @ ( cross ( V(vclk) - vtrans, +1, 1.0, vclk.potential.abstol)) begin
         d[0] = V(vin_d0) > vtrans;
         d[1] = V(vin_d1) > vtrans;
         d[2] = V(vin_d2) > vtrans;
         d[3] = V(vin_d3) > vtrans;
         d[4] = V(vin_d4) > vtrans;
         d[5] = V(vin_d5) > vtrans;
         d[6] = V(vin_d6) > vtrans;
         d[7] = V(vin_d7) > vtrans;
     d[8] = V(vin_d8) > vtrans;
     d[9] = V(vin_d9) > vtrans;
         
        @ ( cross ( V(vclk*10) - vtrans, +1, 1.0, vclk.potential.abstol)) begin // (shifting and output should be here - i think)
       end
      
 
end                            
 
endmodule

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