Piplined Fixed point dividerin verilog

[Hallolo]

Hi every one

iam looking for a piplined fixed point divider, a generic one that i can choose the size of the dividend and divisor , between 2-32 bits. I found a serial one in opencore, but having difficluty with a a piplined one.

If i generate a 32 bit divider using Xilinx coregenerator, will i be able to use it effectively with less than 32 bit inputs say for example if the dividend is 25 bit and divisor is 21 bit. The idea is to have a generic model that can accept variable sizes.

Thanks all , I hope someone can help me in that

 

[lostinxlation]

01010 and 000000000000000000000000000001010 are the same.
Just fill zeros in upper bits. Or if it's signed number, sign extend it.