Pipleline ADC Latency

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musclesinwood

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I am designing a 10-bit pipeline ADC. I have a very basic question about the ADC. I have read in some paper that for a 10-bit pipeline ADC, 6 initial clock cycles are required before the first digital outcome becomes valid. Can some one please tell me how its 6 initial clock cycles required before the first digital outcome becomes valid ?
 

Hi,

You are desgning the ADC...it is a clocked system, so you should know after how much clock cycles the output is valid.

(Just to be sure: you don't talk about delta sigma ADC?)

Klaus
 

Thank You for the response. No it is a Pipeline ADC. What I understood is that each stage gives a valid digital output after one clock cycle. During first half of the clock cycle Sampling will take place. During the second half digitization will take place.
Please correct me if I am wrong.
 

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