Pipeline problem VHDL

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nizdom

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Hi guys! I need some help.

Here is the scenario, in the first timeslot (or one cycle), a value is outputted. Then on the next timeslot, the same signal but it is already updated to anew value. What should I do so that I can use the value from the first timeslot during the second timeslot. Take note that on the second timeslot, the value changes already but what I need is the value from the previous timeslot. Am I gonna store it? How? Help please. newbie here in VHDL. Thanks.
 

nizdom said:
Am I gonna store it? How? Help please. newbie here in VHDL. Thanks.
Click to expand...
VHDL is a hardware description language, how do you store a value for later use (next clock cycle) in hardware?....

use a flip-flop.

input -- DFF -- output

output is delayed by 1 clock
 

ads-ee said:
VHDL is a hardware description language, how do you store a value for later use (next clock cycle) in hardware?....

use a flip-flop.

input -- DFF -- output

output is delayed by 1 clock
Click to expand...

What kind of flip flop should I use? Thaanks!
 

nizdom said:
What kind of flip flop should I use? Thaanks!
Click to expand...

I already showed DFF i.e. D Flip-flop. I'm not going to post the truth table, go look it up in google.
 

Hi,

Here is the scenario, in the first timeslot (or one cycle), a value is outputted.
Click to expand...
I wonder how the output comes at first...

Isn´t it usually this order:
input --> processing --> output?

**
Without knowing what "value" format and what timeslot you are talking about .. the answer can only be very vague.

Klaus
 


you need to learn basics of digital design, ie, how to code combinational and sequential logic, as well as how to connect one to the other to form an actual digital system.
 

ads-ee said:
I already showed DFF i.e. D Flip-flop. I'm not going to post the truth table, go look it up in google.
Click to expand...

Oh I didn't see it! Thaaanks!
 

nizdom said:
What kind of flip flop should I use? Thaanks!
Click to expand...

Don't instantiate individual DFF's. Just assign the value to a signal inside a clocked process. The synthesis tool will add the DFF.
 

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