pipeline for AXI if timing is not met

[sun_ray]

There is an AXI master interacting with an AXI slave. How to pipeline if the timing is not met? Is it sufficient if we pipeline RDATA, RVALID and RREADY? Or some other signals needs to be also pipelined?


Regards

 

[sharath666]

RESP also...

 

[sun_ray]

Are there any other signal other than RRESP,RDATA, RVALID and RREADY needs to be considered?

Regards

 

[kaiserschmarren87]

If you look at the read burst timing diagram then it will give you a clear picture I guess.

 

[sun_ray]

If you look at the read burst timing diagram then it will give you a clear picture I guess.

View attachment 108457

Do you want to mean ARADDR, ARVALID, ARREADY, RVALID, RDATA, RREADY and RRESP all needs to be pipelined?

Regards

 

[kaiserschmarren87]

If you want to have burst data to be read from the slave then you need to have master sending burst address to look for the data at the slave end.
So you need to consider all the signals as shown in the waveform. You can look into the AXI specifications manual for more details. Further you can apply 'Data Interleaving'.