mbago
Newbie level 3
Hello Everybody,
I made a PID controller modul in VHDL, but I have a problem with the integral part. I'm using sfixed datatype. The problem is with this part:
if(I>MAX_Range) then I<=MAX_Range;
elsif(I<MIN_Range) then I<=MIN_Range;
else I<=resize(Ki*error+I,16,-4);
end if;
All of the parameters are sfixed signals and constant. Ki=0.5 error=100
When I load into the FPGA it runs fine up to MAX_Range, but after that the value change to zero and stay zero instead of MAX_Range.
I can't find out what could be the problem. Does anyone have idea?
Thanks,
Marcell
I made a PID controller modul in VHDL, but I have a problem with the integral part. I'm using sfixed datatype. The problem is with this part:
if(I>MAX_Range) then I<=MAX_Range;
elsif(I<MIN_Range) then I<=MIN_Range;
else I<=resize(Ki*error+I,16,-4);
end if;
All of the parameters are sfixed signals and constant. Ki=0.5 error=100
When I load into the FPGA it runs fine up to MAX_Range, but after that the value change to zero and stay zero instead of MAX_Range.
I can't find out what could be the problem. Does anyone have idea?
Thanks,
Marcell