pico second step generator

[wwfieee]

build step generator

anyone have any links/experience building a picosecond generator? or knows how those commercial step generators are based upon?

im trying to build one below 1 nanosecond mark, and the step is from 0 to 5V. so far i only manage around 1.2ns.

thanks

 

[Loq]

pico generator

Hi,

I worked on UWB band pulse generation and I designed a solution based on a specific diode, a Step Recovery Diode. This component can generate rise time step smaller than the ns (can reach 100ps with appropriate design). It Consists in storing charges in the SRD with forward current then discharging it with a reverse current. The SRD stops conducting very quickly and you can use this property to generate sharp steps. Some company like Picosecond Lab or Pulse Lab research should offer such products I think. Or you can try to get some SRD component but maybe it is not easy. Have look on papers of G.H.Stauffer, J.S.Lee and C.Nguyen. Let me know if I cab help you. Good luck.

 

[wwfieee]

hi,

do you have a schematic on how to generate the pulse using SRD? I'm trying to build the step generator, and I will compare it to the commercial picosecond generators. Thanks.

I couldn't find the papers of the people you mentioned.

 

[Loq]

Hi guy,

Sorry but I have no schematic or paper at work. A quick research lead me to a generale paper describing SRD, and pulse generation at follwing adress http://www.medphys.ucl.ac.uk/research/borl/homepages/davek/phd/chapter5.pdf. Effectively the papers I mentionned are no more available on the WEB but they should be on IEEE web site, if you have access to it. You should find a schematic of step generator in this paper. Moreover I remember that some people developed UWB pulser on CMOS technology (MCML tech) like in the paper at the following adress **broken link removed**.
I don't know if it is as efficient and sharp as SRD based solution but maybe you can have a look. I hope I'll help you. If you want, let me know about your design progress, I am interested...

 

[wwfieee]

both links dead. anyway, i've been browsing the web for SRD the whole night and found some pretty interesting infos. however, it seems that not a whole lot of people make them. it makes it hard to get a few samples to test on.

hopefully i am able to get hold of some, then build it to test its speed and step purity. most of the papers done are based on spice simulation or high voltage step. i need steps between -5 to 5V.

in the mean time, i will try to use analog switches and see if i can hit the picosecond risetime. so far, my step generator can only touch 1ns (4.5v) using cmos buffers. the settling is quite good though, less than 5ns.

 

[rfmw]

What is your application? Do you really need the 5Vpp (or even 10Vpp) amplitude?

High-speed SiGe logic can have a rise/fall time approx 50ps-100ps, but only at 800mVpp (ECL amplitude).

 

[wwfieee]

yep i need that full 5V swing. my application is to measure settling time of opamps.

 

[arwooldridge]

You can use avalanche techniques to generate 200 to 400 psec pulses at voltages up to 15 volts for example see
h**p//www.reed-electronics.com/electronicnews/contents/images/323017.pdf
or h**p://www.edn.com/archives/1994/052694/11di5.htm
both are ressurrections of a very old technique.
Regards Anthony