patelvivekv1993
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i am having trouble understanding the ADC module of PIC18F4550
i have configured it as follows
clock 20MHz
PLL prescaler divide by 5
System post scaler
96Mhz/6
Hence my Fosc = 16MHz
now i selected Tad = 16Tosc(101)
also Tacq = 4Tad
hence by adding above two i will get 5us which means sampling frequency is 200KHz?????
and if my sampling frequency is 200KHz(5us) then if i input a square wave of 2KHz(500us) then i think for one cycle of square wave i must get 100samples in which 50samples with 5 and 50 samples with 0??
but it is not happing....
i am using proteus for simulation...
i have configured it as follows
clock 20MHz
PLL prescaler divide by 5
System post scaler
96Mhz/6
Hence my Fosc = 16MHz
now i selected Tad = 16Tosc(101)
also Tacq = 4Tad
hence by adding above two i will get 5us which means sampling frequency is 200KHz?????
and if my sampling frequency is 200KHz(5us) then if i input a square wave of 2KHz(500us) then i think for one cycle of square wave i must get 100samples in which 50samples with 5 and 50 samples with 0??
but it is not happing....
i am using proteus for simulation...