23.9 Single-Supply ICSP™ Programming
The LVP bit in Configuration Register 4L (CONFIG4L<2>) enables Single-Supply ICSP Programming. When
LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied
to the MCLR/VPP pin, but the RB5/PGM pin is then dedicated to controlling Program mode entry and is
not available as a general purpose I/O pin.
LVP is enabled in erased devices.
While programming, using Single-Supply Program- ming, VDD is applied to the MCLR/VPP pin as in
normal execution mode. To enter Programming mode, VDD is applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using
standard high-voltage programming (VIHH applied to the MCLR/ VPP pin). Once LVP has been disabled,
only the standard high-voltage programming is available and must be used to program the device.
Memory that is not code-protected can be erased using either a block erase, or erased row by row,
then written at any specified VDD. If code-protected memory is to be erased, a block erase is
required. If a block erase is to be performed when using Single-Supply Programming, the device must
be supplied with VDD of 4.5V to 5.5V.