Well in regards to the crystal any relatively high frequency signal path should be keep to a minimum.
Stray capacitance, EMI, etc all play a role in the ability to deliver a clean clock signal.
The capacitor across the Vdd and Vss absorbs any EMI or noise on the +5V and GND lines keeping it to a minimum.
Does this make sense?
BigDog
---------- Post added at 05:17 ---------- Previous post was at 05:16 ----------
Glad to hear it. Good clocks and power supplies are essential with almost any MCU.