Physical Verification with TSMC65nm CRN65LP PDK

Hello,

This posting is similar to an earlier posting:

https://www.edaboard.com/showthread.php?280164-Physical-verification-with-TSMC-CRN65LP-v1-7a-PDK

I do not have the hcells file.

How do I create it or get it ? Can I use the Assura hcells file in Calibre setups ?

What is it used for and what is the purpose of this cell file ?

Can I create it during LVS of my design - is it specific to each design ? Do I create it for the design ?

Am I missing this file ?

Thank you.

Now I was told for my version of Calibre 2017, I have to do the following for this PDK:


In LVS rule file add:


LAYOUT CELL LIST pcells “rf component here*” “rf component here*”
LAYOUT PRESERVE CELL LIST pcells


In PEX rule file add:


Use XCELL file, add -I option at end.

rf component here* rf component here -I
rf component here* rf component here -I


Where rf component here is the pcell that should not be double counted (if the rf model of an nmos or pmos)


I assume I am adding all the RF components, transistors, passives (caps) etc in the LVS rule file that I have in the foundry provided PEX XCELL file.

Is this correct ?

What is an HCELL file ? What is an XCELL file ? What is the purpose of the source added file ?

Thank you.

no one uses tsmc65nm PDK here ?