That's basically what my first PD design was. Sure 800MHz would be great, but my sampling frequency is 40MHz (limited by the ADC).Can you just get the two positive-going zero crossings
and run a timer, and then do the arithmetic? Seems like
a 800MHz clock would get you better than 1 degree
resolution. Accuracy might have to do with other things
like zero-crossing-compare jitter / offsets as well.
Hi,
DFT or correlation comes into my mind.
Not that difficult math..but good precision, even for noisy signals.
Klaus
However given your unknown frequency and duty cycle variation this does seem like a processor may be better. FPGA's work very well on continuous streams of data, harder when other variables and states start entering the equation.
I agree that processor is simpler. Additional logic (e.g. FPGA) is however needed due to the high sample rate, unless you have a fast signal processor that can stream in samples at 40 MHz. In this situation it's always an option to perform all sequential processing in FPGA, particularly if no suitable processor is present in the sub system or you can't provide an interface with sufficient throughput.
A final idea would be to do linear interpolation of the data-points around the zero crossing to improve timing resolution and noise immunity to an extent.
2MHz frequency on 40Msps means you have 20 samples per cycle. Thus maximum phase resolution possible is 360/20 per sample. So to get 5 degrees you need to upsample or design fractiona delay. I suggest Farrow filter and a feedback loop based on phase error detector using the two peaks then find out how much delay is there when loop converges
I don't agree. You get a much higher phase resolution by I/Q demodulation, only limited by the ADC resolution and signal noise.2MHz frequency on 40Msps means you have 20 samples per cycle. Thus maximum phase resolution possible is 360/20 per sample.
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