The rightmost invert-gate pulls the D pin hi or low, to drive flip-flop operation in a correct way that divides by 2.
Usually a divide-by-2 schematic omits the invert-gate and connects D pin to Not-Q pin.
However we might surmise that the invert-gates together create a slight delay function, seeing there are buffers in your schematic labelled with a delay function.
Fast speeds (as 400MHz) can create delays simply due to propagation time in switching devices. Whereas, at slow speeds we usually see capacitors or inductors arranged clearly and understandably to form a delay network.